1 Introductionof VLSI

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ECE357: Introduction to VLSI CAD

Electrical Engineering & Computer Science Northwestern University

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Prof. Hai Zhou

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Logistics Time & Location: MWF 11-11:50 TECH L160

Instructor: Hai Zhou haizhou@ece.northwestern.edu Oce: L461 Oce Hours: W 3-5P

Teaching Assistant: Chuan Lin Texts: VLSI Physical Design Automation: Theory & Practice, Sait & Youssef, World Scientic, 1999. Reference:2

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An Introduction to VLSI Physical Design, Sarrafzadeh & Wong, McGraw Hill, 1996. Grading: Participation-10% Project-30% Midterm-30% Homework-30% Homework must be turned in before class on each due date, late: -40% per day Course homepage: www.ece.northwestern.edu/~haizhou/ece357

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What can you expect from the course Understand modern VLSI design ows (but not the details of tools) Understand the physical design problem

Familiar with the stages and basic algorithms in physical design Improve your capability to design algorithms to solve problems Improve your capability to think and reason3

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What do I expect from you Active and critical participation

speed me up or slow me down if my pace mismatches yours Your role is not one of sponges, but one of whetstones; only then the spark of intellectual excitement can continue to jump over Read the textbook

Do your homeworks You can discuss homework with your classmates, but need to write down solutions independently4

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VLSI (Very Large Scale Integrated) chips VLSI chips are everywhere computers

commercial electronics: TV sets, DVD, VCR, ... voice and data communication networks automobiles

VLSI chips are artifacts they are produced according to our will ...

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Design: the most challenging human activity Design is a process of creating a structure to fulll a requirement Brain power is the scarcest resource Delegate as much as possible to computersCAD Avoid two extreme views:

Everything manual: impossiblemillions of gates Everything computer: impossible either

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Design is always dicultA main task of a designer is to manage complexity Silicon complexity: physical eects no longer be ignored resistive and cross-coupled interconnects; signal integrity; weak and faster gates reliability; manufacturability System complexity: more functionality in less time gap between design and fabrication capabilities desire for system-on-chip (SOC)7

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CAD: A tale of two designs Targethardware design

How to create a structure on silicon to implement a function Aidsoftware design (programming) How to create an algorithm to solve a design problem Be conscious of their similarities and dierences

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Emphasis of the course Design ow

Understand how design process is decomposed into many stages What are the problems need to be solved in each stage Algorithms

Understand how an algorithm solves a design problem Consider the possibility to extend it Be conscious and try to improve problem solving skills9

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Basics of MOS Devices The most popular VLSI technology: MOS (Metal-Oxide-Semiconductor).

CMOS (Complementary MOS) dominates nMOS and pMOS, due to CMOSs lower power dissipation, high regularity, etc. Physical structure of MOS transistors and their schematic icons: nMOS, pMOS. Layout of basic devices: CMOS inverter CMOS NAND gate CMOS NOR gate10

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MOS Transistors gatedrain source conductor (polysilicon) insulator (SiO2) drain n n gate

psubstrate ntransistor

diffusion

The nMOS switch passes "0" well.

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gate

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substrate

schematic icon

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source

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conductor (polysilicon) insulator (SiO2)

source substrate

nsubstrate ptransistor

diffusion

schematic icon

The pMOS switch passes "1" well.11

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A CMOS InverterMetal VDD Polysilicon Metaldiffusion contact pMOS transistor

nMOS transistor

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GND

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A 1 0

B 0 1

pchannel (pMOS)

nchannel (nMOS) GND

layout12

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A CMOS NAND GateMetal VDD Diffusion Polysilicon C A

GND

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A 0 0 1 1

m o cVDD

B C 0 1 1 1 0 1 1 0

CB

GND

layout13

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A CMOS NOR GateMetal VDD Polysilicon

A

C

GND

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A 0 0 1 1

m o cVDD

B C 0 1 1 0 0 0 1 0

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C

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GND

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Current VLSI design phases Synthesis (i.e. specication implementation)

1. High level synthesis (459 VLSI Algorithmics) 2. Logic synthesis (459 VLSI Algorithmics) 3. Physical design (This course)

Analysis (implementation semantics) Verication (design verication, implementation verication) Analysis (timing, function, noise, etc.) Design rule checking, LVS (Layout Vs. Schematic)15

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Physical Design Physical design converts a structural description into a geometric description. Physical design cycle: 1. Circuit partitioning 2. Floorplanning

3. placement, and pin assignment 4. Routing (global and detailed) 5. Compaction16

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Design StylesIssues of VLSI circuits

Performance

Area

Full custom

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Different design styles

Standard cell

Gate array

FPGA

CPLD

SPLD

SSI

Performance, Area efficiency, Cost, Flexibility

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Full Custom Design Style

Data path PLA

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ROM/RAM

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overthecell routing

A/D converter

Random logic

I/O pads

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Standard Cell Design StyleD A C B

A

B

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library cellsCell A

Cell C

Cell D

Feedthrough Cell

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Gate Array Design Style

I/O pads

pins

prefabricated transistor array

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FPGA Design Style

logic blocks

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routing tracks

switches Prefabricated all chip components21

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SSI/SPLD Design Stylex1 y1 x2 y2 x3 y3 x4 y474LS86 x1 y1Vcc

74LS02Vcc

74LS00

Vcc

x3 y3

x2 y2

GND

F=

4 i=1

xi

yi

(a) 4bit comparator.

x1 y1 x2 y2 x3

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y3

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m o cx3 y3 x4 y4

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(b) SSI implementation.

AND arrayx1 y1 x2 y2

OR array

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(c) SPLD (PLA) implementation.

(d) Gate array implementation.

F

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Comparisons of Design StylesCell size Cell type Cell placement Interconnections Full custom variable variable variable variable Standard cell xed height variable in row variable

* Uneven height cells are also used.

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